Applications of Metric Embedding to Regular Ic Optimization

Applications of Metric Embedding to Regular IC Optimization Ph. D. Dissertation Padmini Gopalakrishnan Department of Electrical and Computer Engineering Carnegie Mellon University Prof. Lawrence T. Pileggi, Chair In digital IC design methodologies, the design netlist is typically modeled as a graph or hypergraph, and information about its structure or topology is often used in optimization. Often this information about graph structure tends to be local in nature. Where it is more global in scope, this information is usually computationally expensive to obtain. Metric geometry provides some very powerful tools and techniques for reasoning about the global topology of graphs, and it is conceivable that the application of these concepts could result in better design optimization. This is especially true of regular ICs where the underlying implementation fabric has a lot of structure, a good understanding of which could effectively guide optimization decisions. In this dissertation, we focus on the placement problem for Field Programmable Gate Arrays (FPGAs) as one concrete example of an optimization problem that could benefit from a better understanding of the global topology of both netlists and regular IC architectures. It is well known that performance on FPGAs is dominated by the routing architecture rather than wirelength. Therefore, it is critical that this relationship be modeled during placement and physical design. To this end, we first develop an analytical framework to model this relationship using concepts from graph embedding and metric geometry. Using these models, we then propose a new architecture-aware approach to initial FPGA placement. The philosophy behind our approach is similar to wirelength minimization during global placement for ASICs, except that we seek to minimize an objective that correlates well with FPGA routing delays. At the heart of our approach, CAPRI, is the idea that any placement algorithm can be viewed as an embedding of a graph representing the netlist into a chosen metric space. In particular, we develop an analytic metric of distance in terms of delays along the FPGA routing grid, and use it to build a metric space that is appropriate for FPGAs. We then formulate the embedding of a netlist into this metric space as a binary quadratic assignment problem. This analytical formulation is cognizant of both the discrete nature of the FPGA placement problem, as well as the complex relationship between delay and the routing architecture. While our problem formulation has a convex objective, the solution space is discrete and therefore non-convex. This precludes the direct application of convex optimization methods. Our next step is, therefore, to develop an effective heuristic technique to find a good solution. Our strategy uses several effective approximations, including matrix decomposition and online bipartite matching. These approximations are crucial for the practical application of our placement formulation. We also propose a placement methodology where CAPRI is used to produce an initial architecture-aware placement solution, and local optimization using existing move-based techniques is subsequently used to improve specific critical paths and routability.